1. Field of the Invention
This invention relates to a semiconductor memory device and a memory system, and more particularly to a semiconductor memory device with memory cells each of which have a charge accumulation layer and a control gate.
2. Description of the Related Art
A multilevel NAND flash memory has been known. A multilevel NAND flash memory is a NAND flash memory which enables each memory cell to hold 2 or more bits of data. For example, in a 4-level NAND flash memory, one memory cell holds 2 bits of data. In an 8-level NAND flash memory, one memory holds 3 bits of data. Such configurations have been disclosed in, for example, U.S. Pat. No. 5,847,999.
If a memory block has 64 word lines and 32K bit lines in a NAND flash memory, the capacity of a 2-level NAND flash memory is 256 Kbytes, the capacity of a 4-level NAND flash memory is 512 Kbytes, and the capacity of an 8-level NAND flash memory is 768 Kbytes. Here, a memory block is a set of memory cells. The data in the memory cells in the same memory block are erased simultaneously.
Furthermore, the NAND flash memory uses a method of, for example, when recording video, securing a logical space whose size is somewhat large and which has consecutive logical addresses and recording video in the logical space. The logical space is known as an allocation unit (AU). The size of the AU is generally set at a power-of-two value.
For example, in a multilevel NAND flash memory, such as an 8-level NAND flash memory, its memory capacity may not be expressed by a power-of-two value. Accordingly, in the 8-level NAND flash memory, the size of the AU does not coincide with an integral multiple of the size of the memory block. As a result, the multilevel NAND flash memory needs the operation of copying data and therefore may have to stop recording video for a while, which is a problem.